1. Field of the Invention
The present invention is generally related to general purpose, stored program, digital computers and more particularly relates to computer architectures having maintenance paths to improve system reliability.
2. Description of the Prior Art
A key element in the design of today's digital data processing equipment is the factor of testability. In the past twenty years, the complexity of integrated circuits and computer systems has increased exponentially with time. As a result, current computer systems often have internal circuitry which cannot be controlled or observed from accessible I/O pins.
One technique for improving the testability of today's computer systems is to provide maintenance circuitry within the computer system which allows the internal circuity to be controlled and observed. An examples of this technique is a Serial SCAN architecture. SCAN providing serial scan registers and serial scan paths within the design. These components allow the internal nodes to become controllable and observable via a plurality of serial scan input ports and a plurality of serial scan output port.
A typical method of testing a system which employs SCAN is to use computer generated serial scan test vectors. The scan registers are first placed in a "test" mode. Then, a serial scan vector is serially clocked into the scan registers via a scan-data-in port. The scan registers are then switched into functional mode. At this point, the data contained in the registers trickle through the logic between registers until they reach the input of a receiving scan register. The test controller then clocks the functional clock once capturing the data that just trickled through said logic. The resulting contents are serially clocked out via a scan-data-out port and compared to an expected result. This process is repeated until a predetermined fault coverage is reached. This process is carried out via high level interfaces connected to external test equipment, controllers or even operating systems. Therefore, costly test hardware and/or software is required to utilize this methodology.
The SCAN methodology can be coupled to a Built-in-Self-Test (BIST) algorithm which allows the computer system to perform self tests. However, BIST algorithms required either a special BIST processor within the design or the use of external test hardware to perform the tests. In addition, BIST requires that the computer system be placed in a "test" mode thereby allowing the registers within the design to be serially scanned.
Finally, the SCAN and/or BIST techniques can be combined with self correcting algorithms. That is, once a fault is detected, algorithms can be used to isolate which devices or interconnect lines within the system are faulty. This allows the system designer to design in redundant components which can replace the detected faulty components. However, systems which employ this methodology require the backup components to be activated through higher level interfaces, controllers or even operating systems. Therefore, costly test hardware and/or software is required to utilize this methodology. In addition, these systems require that the system be taken out of the functional mode and placed into a "test" mode in order to detect any faults and to replace any faulty components. This results in a period of time where the system is functionally inoperable.
Finally, some computer systems employ maintenance architectures which provide maintenance processors and maintenance interfaces. The maintenance processors are responsible for directing all maintenance activity within the computer system. The maintenance interfaces are used to direct the maintenance commands from the maintenance processors to the various computer components. The typical mode for testing the maintenance processor and maintenance interfaces would be through scan vectors as discussed above.